Scrypt fpga jobs
...develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action...
We wish to setup a system similar to attached. We have installed it at We need to have the system to talk to VPS servers we sell to our clients currently the user login page does not work and there is no scrypt for the server to supply the details for the page. We will manually setup the masternode or staking coin for the customer and the genkey is changed will need to go into the coins config file. Please contact if interested for further clarification.
I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA.
Your task is to create a KiCad library for the part LCMXO2-256ZE-1UMG64C and a KiCad footprint for it. On Digikey it is this part: Then you create a breakout board for it, see the attached file for an example how it should look like: The FPGA in the center, and then pin headers to break out every connected FPGA pad, and a label for each pin on the silkscreen. For the pad names see page 39 for 64-ball ucBGA : ~/media/LatticeSemi/Documents/PinPackage/ The pinout for the MachXO2-256, see this document, package UCBGA64: The labels on the silkscreen must be from the column "Pin/Ball Function", but you must connect it to the pads
Create new working template look. Only look. (No functionality) I need integrate old design (renew or remake) to new page tradersmonitor.com. I have all images and old source code if you need. Before it looks like this on screenshot. Everything is working. There is only work on look. Banners, subpages, every functions is done by scrypt and need just make look for it Need : Make whole web (and subpages) look like something like on screenshot. Working. NO BUDGET INCREASION AFTER BID. Old page and page on screenshot is totaly the same. Every function is the same and is editable in admin panel.
Here's an Android Studio project: I want it to use these two native libraries: I've already managed to add a scrypt support by adding "" files here: but as far as I understand that is a somewhat hacky approach while the proper way is to install NDK, then add native libraries source code to project's github repo and instruct Gradle to compile them. So that is what I want to be done. More precisely, I want you to: - fork an Android Studio project on GitHub and make all the modifications outlined above - (if needed) write a step-by-step manual which I can use to correctly compile a project
build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Acc...symbol on a schematic diagram and connected together using wires. Accompanied with each unit should be a functional waveform for verification. It is also mandatory that any four units be connected together or working together using only Verilog HDL, then that design can be placed as a symbol on a schematic diagram. Use Quartus to build your project. Your design need to also be verified on the DE2-115 FPGA Altera...
Need experts in electrical engineering field especially in FPGA and Embedded systems that are also skilled in vhdl. Please look at the link for more details. Refer to the intro pdf for project requirements and deliverables. Need complete project done even the scripts for presentation and technical report.
I want to create my own Coin and also exchanger on it. Modules: Admin Panel, User registration, Charts to display Price Changes, Wallet. The new currency should be made on Scrypt Algo, Market cap will be 2.1MIllion Exchanges: ONLY MY CURRENCY TO BTC MY CURRENCY TO LTC MY CURRENCY TO ETH MY CURRENCY TO ETC MY CURRENCY TO BCC
I want to create my own Coin and also exchanger on it. Modules: Admin Panel, User registration, Charts to display Price Changes, Wallet. The new currency should be made on Scrypt Algo, Market cap will be 2.1MIllion
i want to implement three phase locked loop implemented in simulink
Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs.
I need a tutor for fpga programming in vhdl. I have made some projects but they need to be corrected. I'm working on Xilinx Spartan-6.
...Connect a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial monitor while the bit received by the UNO (from the FPGA) should be displayed inside the serial monitor window. You should do the 5th question 5. Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutto...
Objective: Design a coprocessor that finds square of an integer (x2), finds square-root of an integer (x0.5), converts an uppercase word to lowercase word, performs floating-point addition, and performs floating-point multiplication. Implement the design on a SoC (System on a Chip) using XPS and SDK tools of Xilinx. Requirements: (80 Points) ...square-root, uppercase to lowercase conversion, floating-point addition, and floating-point multiplication). 2. Implement the coprocessor design using a system (processor, memory, user logic, and slave registers) that is built using Xilinx Platform Studio (XPS) 3. Using the Xilinx SDK, write a software routine to test (at least two test cases per operation) the coprocessor that is designed using an FPGA SoC and implemented on Nexy...
Hi muhammadumairuet, I noticed your profile and would like to learn your project "Grid Tied Multilevel Inverter with Power Quality Monitoring using myRIO FPGA ". I have myRIO and I'm student of Master course. We can discuss any details over chat. I'm from Brasil, and would like to reproduce your work; Thank you for help. Best regard;
I need someone to write a scrypt that will scrape data off websites. Specifically for bitcoin data, so the information is not hard to find and access. I just need a quicker more automated way to do so to a CVS file. If possible, it would be great if it was automated. I am not sure what the price point of a project like this would be, bit please contact me if you are interested. It does not have to be python. Let me know if this would cost more.
Need Platform and Bitcoin Coin, along with website. Professionals only. Need creative and fast work. Need you to: 1 Create the cryptocurrency (32 Mill max-coin supply algorithm Sha 256, scrypt x11 x13 2 Create the Website (front face) Html, Css, jquery and bootstrap ( mobile ready) 3 Develop and link the backend with the Website. I want to use Codeigniter. Show me your work that you have already done. Thank you.
I need developer who can create mining pool for Scrypt Pos/pow. but i need it urgent thanks
...Connect a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial monitor while the bit received by the UNO (from the FPGA) should be displayed inside the serial monitor window. 5. Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depre...
Digital clock with Pmod OLED rgb display connected to FPGA Nexys4 DDR based on VHDL programming , including Digital clock package having the features of time sitting , alarm sitting ( on-off , a standard ringtone and flashing leds-2 LED CHASER- ) , stopwatch sitting By default that display current date and time on two lines Day dd/mm/yyyy : MON 17/02/2017 hh:mm:ss (AM/PM) : 11:23:55 AM If i put the swich 1 that display : DATE SET ( nothing else displayed on the screen ) then i have 5 boutons lets say B1 B2 B3 to select day , month or year then B4 B5 to increment and decrement Switch2 display TIME SET then by the same process B1 B2 B3 to select hour , minutes and seconds then B4 and B5 to increment and decrement ALARM : Switch3 : on-off Switch 4 display AlARM SET...
Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depressed and released, the FPGA sends a bit string of 16 bits to the UNO for display. Depending on the XOR result on the 16 bits, the bit string sent from the FPGA is either the same as the received bit string or the 1’s complement of the received bit string. The data transfer should be as fast as possible. The original bit string may be hard-coded inside the UNO code or input from a serial monitor
...connects to a micro USB socket. The redundant USB socket can be removed from the design. c. Connect one SPI bus of the MCU to the PCM2707, and another SPI bus to the FPGA/Flash memory. Add a sliding switch to change the FPGA’s boot up mode between self-boot via Flash memory (SPI master mode), or waiting to be programmed by the MCU (SPI slave mode). The existing SPI connection between the FPGA and PCM2707 (PCM_MS/MC/MD) can be removed. d. Connect an I2S bus (full duplex) of the MCU to the FPGA. e. Add a sliding switch to MUX the source to the I2S DIN input of PCM2707 between its own I2S DOUT and the DIN output from the FPGA. f. The nSuspend, PSEL and Host pins of PCM2707 can be tied high, while the FSEL pin can be tied low. Since the PCM2707 should ...
...Connect a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial monitor while the bit received by the UNO (from the FPGA) should be displayed inside the serial monitor window. 5. Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depre...
...Connect a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial monitor while the bit received by the UNO (from the FPGA) should be displayed inside the serial monitor window. 5. Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depre...
...Connect a DE0-Nano FPGA board to a UNO board using two jumper wires for data transfer and one wire to connect their grounds. Write codes that allow the microprocessor to use one wire to send a bit over to the FPGA which inverts the bit and sends it back to the microprocessor using the other wire. The bit value to be sent out from the UNO should be input from the serial monitor while the bit received by the UNO (from the FPGA) should be displayed inside the serial monitor window. 5. Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is de...
I have to do real time face detection on FPGA. I want someone intellectual to do it. Hardware implementation is required.
SHA3 (Keccak) is fast on FPGAs: I'm looking for the best price/performance ratio for a SHA3 implementation on FPGAs.
i want verilog or vhdl code which can be implement on xilinx fpga
i want verilog or vhdl code which can be implement on xilinx fpga
I have a requirement of interfacing Ethernet with FPGA and then connect it to PC and communicate: What I am expecting: 1. Details o hardware implementation 2. Information on which mode Ethernet will be working 3. Details on VHDL code for getting packets from PC and then saving those Packets in memory. Also Sending packets to PC. 4. PC Side implementation of sending and receiving packets.
I am looking for a person to guide me on which FPGA evaluation kit to be bought for learning RAM interfacing, gigabit ethernet, SD Card and JESD204 interface. This project can lead to the long term project that will involve development of codes and hardware.
i need a block explorer for crypto currency which is on scrypt Hybrid algorithm, Here is the source code: A sample explorer is , you can even provide any another blockexplorer as well , but i have to see the design first, only those people bid who already did some projects in this
Integración de electrocardiografo y electromiografo haciendo uso de una FPGA para filtrado digital, procesamiento de datos y envío de información por medio de HC06 al celular.
We are a software company in the EDA industry. Our users are FPGA or ASIC engineers working in VHDL and/or SystemVerilog. We are looking for several people to create and distribute online video content for us on a regular basis. What skills do you need? - knowledge on hardware design projects - coding in VHDL and/or SystemVerilog - professional verbal and written English How can you apply? - step 1: register for a free trial software at !!! IMPORTANT to fill into the online form: - Company website = Freelancer.com - Country = Belgium - step 2 : get basic experience with the first use of our product - step 3 : Select either the "VHDL Tutorial" or "Verilog Tutorial" project. Create a video review of you completing one of these projec...
Hello we need POW/POS coin Total Supply: 250000000 Air DROP 2% of coins=500000 • Coin Algorithm Scrypt (PoW/PoS) • Coin Abbreviation : ATRN • Total PoW block : 250000 • PoW block reward : 10 BCC • Block Spacing : 2mintus • Minimum Stake Age : 10 Days • Maximum Stake Age : 70 Days premined 70%: need web wallet and desktop wallet and mobile also need integration to our website
Hi. Do you have a gerber file Gerber file for ASIC miner or scrypt? You wanted to do https://www.freelancer.com/projects/Mathematics/Create-Gerber-file-for-ASIC/
Hi, We are engineering consultancy and IT firm. We need some IT guys for some small tasks. We would make long term relationship with the best one. Below is the task details: The total word count is limited around 2000 (±10%). 1. Introduction to Nios II softcore processor: (30%) A simple design and build a Nios II softcore processor on FPGA. Write a short, properly structured technical report. 2. Customisation of Nios II softcore processor: (30%) An introduction to customising Nios II softcore processor using Qsys. Write a short, properly structured technical report. 3. Computer peripherals: (40%) A simple design exercise of configuring peripherals for Nios II softcore processor. Write a short, properly structured technical report. Submissio...
Design an 8-bit coprocessor that can find square of an integer (x^2), find square-root of an integer (x^0.5), and converts a capital letter to a small letter and implement it on the Nexys 4 FPGA board using the VHDL design feature of Xilinx ISE design studio. More details in the doc please.
The project is realted to Computational Neural Networks
THis must implement on quartus( altera FPGA cyclone IV)
calculataion area in black and white image on fpga ( cyclone IV)
I want to create a working stratum using the yiimp protocol. I have tried to implement this myself, but I don't have the skills to fix all the bugs. You will be using the yiimp framework. (). We can talk about the details, but you should be relatively familiar with how this software works as well as how bitcoin mining works...yiimp framework. (). We can talk about the details, but you should be relatively familiar with how this software works as well as how bitcoin mining works. AWS is probably the best place to set this up; please have Linux and AWS experience. This job will be done when yiimp is successfully setup with auto exchange payments using bitcoin with a selection of x11 and scrypt wallets setup and ready to use.
