Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    246 jobs found, pricing in SGD

    To simulate in LTspice or MultiSim a stair step wave within the sine wave generating circuit the circuit design using only analogue components like R, C, Op-Amp but no digital components like microcontroller. Task details will be provided to competed bidders only. If you have good command using above mentioned softwares then bid only. Pls note that the task is to complete in one day only not mor...

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    Need someone who is efficient in ARM processor programming for an urgent assignment

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    I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not...

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    I want to design a circle through the Proteus program with the code. I have the code but I do not know the results show.

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    Verilog coding 5 days left

    Verilog code of Simplified DES algorithm

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

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    Serializer & Desrializer Implementation using ZC706 and MTX

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    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou...

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    I need a simple MIPS code. I will send you the task. I need it in an hour.

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    Hi there Please check the document

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    FPGA Design 1 day left

    Hi there Please check the document!

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    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

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    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    200418_Verilog 17h left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $66 - $106
    Sealed
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    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send...

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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

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    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

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    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

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    translate c++ code in systemc and implement constrained random verification methodology.

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    translate c++ code in systemc. and implement constrained random varification methodology.

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    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

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    translate a C++ code in systemc module.

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    you have to translate C++ code in systemc language.

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    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

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    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

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    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

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    Circuit at logism Ended
    VERIFIED

    implement a digital circuit in Logisim for a door lock.

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    expert in vivado and vhdl needed asap

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    there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do.

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    we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b)

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    I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte...

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    Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU

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    using four bit ALU, given two numbers A and B we need to find if A is divisible by B

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    I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.

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    Preciso de um aplicativo para Android. Já tenho desenho para ele, apenas preciso que seja construído.

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    Details later.. I will check your BASIC.. And then recruit You

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    programming mplab Ended
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    programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent

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    Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks

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    Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks

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    Small project on computer architecture

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    State Machine and Timing Diagram for Embedded System. More details to be provided.

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    In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov...

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    Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL.

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    NS3 simulation using c++ and ubunto NS3 simulator

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    i need this simulation for ns3 using c++

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    Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview

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    1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output

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    Design a serial interface using Python for communication with FPGA.

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