Verilog / VHDL jobs

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About Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    246 jobs found, pricing in SGD
    Circuit Simulation - 26/04/2018 05:56 EDT 6 days left
    VERIFIED

    To simulate in LTspice or MultiSim a stair step wave within the sine wave generating circuit the circuit design using only analogue components like R, C, Op-Amp but no digital components like microcontroller. Task details will be provided to competed bidders only. If you have good command using above mentioned softwares then bid only. Pls note that the task is to complete in one day only not mor...

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    $44 (Avg Bid)
    $44 Avg Bid
    11 bids
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    Need an ARM processor programming expert - 26/04/2018 05:17 EDT 6 days left

    Need someone who is efficient in ARM processor programming for an urgent assignment

    C Programming Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $80 (Avg Bid)
    $80 Avg Bid
    5 bids
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    Verilog Code for Fast Fourier Transform 5 days left

    I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not...

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $185 (Avg Bid)
    $185 Avg Bid
    14 bids
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    Traffic Light Priority Control For Emergency Vehicles 5 days left

    I want to design a circle through the Proteus program with the code. I have the code but I do not know the results show.

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $175 (Avg Bid)
    $175 Avg Bid
    19 bids
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    Verilog coding 5 days left

    Verilog code of Simplified DES algorithm

    Computer Security Software Architecture Verilog / VHDL
    $21 (Avg Bid)
    $21 Avg Bid
    7 bids
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    Convert a python program to vhdl 4 days left
    VERIFIED

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    Arduino CUDA Python Software Architecture Verilog / VHDL
    $400 (Avg Bid)
    $400 Avg Bid
    10 bids
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    Serializer & Desrializer Implementation using ZC706 and MTX___ 4 days left
    VERIFIED

    Serializer & Desrializer Implementation using ZC706 and MTX

    FPGA Verilog / VHDL
    $498 (Avg Bid)
    $498 Avg Bid
    2 bids
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    Modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) 4 days left
    VERIFIED

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou...

    Electrical Engineering Embedded Software FPGA Microcontroller Verilog / VHDL
    $240 (Avg Bid)
    $240 Avg Bid
    5 bids
    Bid now
    build a very simple MIPS code 2 days left

    I need a simple MIPS code. I will send you the task. I need it in an hour.

    Assembly C Programming C++ Programming Java Verilog / VHDL
    $27 (Avg Bid)
    $27 Avg Bid
    9 bids
    Bid now
    FPGA Design and Asic 1 day left

    Hi there Please check the document

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $45 / hr (Avg Bid)
    $45 / hr Avg Bid
    10 bids
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    FPGA Design 1 day left

    Hi there Please check the document!

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $20154 (Avg Bid)
    $20154 Avg Bid
    6 bids
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    Floating Point on DSP48E1 1 day left

    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

    FPGA Verilog / VHDL
    $313 (Avg Bid)
    $313 Avg Bid
    6 bids
    Bid now
    MIPS Computer Design by Verilog HDL 21h left
    VERIFIED

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    Assembly Digital Design Engineering FPGA Verilog / VHDL
    $182 (Avg Bid)
    $182 Avg Bid
    18 bids
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    need to implement an ieee paper using verilog or vhdl. -- 2 19h left

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    Verilog / VHDL
    $159 (Avg Bid)
    $159 Avg Bid
    10 bids
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    200418_Verilog 17h left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    Electrical Engineering Electronics Verilog / VHDL
    $66 - $106
    Sealed
    $66 - $106
    4 bids
    Bid now
    Conceive SDR GnuRadio blocs 13h left
    VERIFIED

    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send...

    Electrical Engineering Electronics Linux Microcontroller Verilog / VHDL
    $1287 (Avg Bid)
    $1287 Avg Bid
    6 bids
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    Implementing Bit stuffing in verilog 9h left

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $39 (Avg Bid)
    $39 Avg Bid
    11 bids
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    Edge detection by using laplacian 3h left

    I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

    C Programming C++ Programming CUDA Software Architecture Verilog / VHDL
    $197 (Avg Bid)
    $197 Avg Bid
    1 bids
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    plc program and hmi design Simulation Ended

    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

    Electrical Engineering Electronics Engineering Microcontroller Verilog / VHDL
    $27 (Avg Bid)
    $27 Avg Bid
    14 bids
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    develop Simple SW to write on the IC Card/Server Ended

    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

    C Programming Electronics Microcontroller PCB Layout Verilog / VHDL
    $377 (Avg Bid)
    $377 Avg Bid
    4 bids
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    translate C++ code in systemc. Ended

    translate c++ code in systemc and implement constrained random verification methodology.

    C Programming C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)
    $36 (Avg Bid)
    $36 Avg Bid
    4 bids
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    build a software Ended

    translate c++ code in systemc. and implement constrained random varification methodology.

    C++ Programming Software Architecture Verilog / VHDL Very-large-scale integration (VLSI)
    $27 (Avg Bid)
    $27 Avg Bid
    1 bids
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    Create a DLX Data Path Using VHDL Ended

    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

    Assembly FPGA Microcontroller Software Architecture Verilog / VHDL
    $236 (Avg Bid)
    $236 Avg Bid
    8 bids
    Bid now
    build a software Ended

    translate a C++ code in systemc module.

    C Programming C++ Programming Verilog / VHDL
    $41 (Avg Bid)
    $41 Avg Bid
    3 bids
    Bid now
    convert the C++ language code in systemc. Ended

    you have to translate C++ code in systemc language.

    C Programming C++ Programming Software Architecture Verilog / VHDL
    $44 (Avg Bid)
    $44 Avg Bid
    3 bids
    Bid now
    Do VHDL project on the ModelSim Ended
    VERIFIED

    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $203 (Avg Bid)
    $203 Avg Bid
    11 bids
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    SoundLocator Ended

    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

    Android Electronics FPGA Java Verilog / VHDL
    $822 (Avg Bid)
    $822 Avg Bid
    14 bids
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    OpenCL FPGA Code modification Ended

    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

    C Programming Cryptography FPGA OpenCL Verilog / VHDL
    $2986 (Avg Bid)
    $2986 Avg Bid
    6 bids
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    Circuit at logism Ended
    VERIFIED

    implement a digital circuit in Logisim for a door lock.

    Circuit Design Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $33 (Avg Bid)
    $33 Avg Bid
    3 bids
    Bid now
    expert in vivado vhdl needed Ended
    VERIFIED

    expert in vivado and vhdl needed asap

    Electrical Engineering Engineering FPGA Microcontroller Verilog / VHDL
    $33 (Avg Bid)
    $33 Avg Bid
    8 bids
    Bid now
    digital logic design circuit in logisim Ended
    VERIFIED

    there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do.

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    $149 (Avg Bid)
    $149 Avg Bid
    9 bids
    Bid now
    digital circuit in logisim Ended
    VERIFIED

    we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b)

    Circuit Design Electrical Engineering Electronics Microcontroller Verilog / VHDL
    $28 (Avg Bid)
    $28 Avg Bid
    6 bids
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    Signal Peak Detector, Digital Design - Command Processor Ended

    I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte...

    Electrical Engineering Electronics Engineering Matlab and Mathematica Verilog / VHDL
    $61 (Avg Bid)
    $61 Avg Bid
    7 bids
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    Circuit in Logism Ended

    Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
    $86 (Avg Bid)
    $86 Avg Bid
    8 bids
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    Logisim Digital Logic Design Ended

    using four bit ALU, given two numbers A and B we need to find if A is divisible by B

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $104 (Avg Bid)
    $104 Avg Bid
    15 bids
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    Neural Network on an FPGA Ended

    I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.

    C Programming FPGA Machine Learning Neural Networks Verilog / VHDL
    $195 (Avg Bid)
    $195 Avg Bid
    5 bids
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    aplicativo para Android Ended

    Preciso de um aplicativo para Android. Já tenho desenho para ele, apenas preciso que seja construído.

    Android Mobile App Development Verilog / VHDL Volusion
    $64674 (Avg Bid)
    $64674 Avg Bid
    10 bids
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    CRYPTO MINING using VHDL in FPGA Ended

    Details later.. I will check your BASIC.. And then recruit You

    Digital Design FPGA Mining Engineering Verilog / VHDL
    $2765 (Avg Bid)
    $2765 Avg Bid
    2 bids
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    programming mplab Ended
    VERIFIED

    programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent

    Arduino C Programming C++ Programming Microcontroller Verilog / VHDL
    $287 (Avg Bid)
    $287 Avg Bid
    18 bids
    Bid now
    Experts on Communication system, Digital Signal Processing, and Matlab needed 2 - 12/04/2018 18:48 EDT Ended
    VERIFIED

    Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks

    Electrical Engineering Engineering Matlab and Mathematica Telecommunications Engineering Verilog / VHDL
    $41 (Avg Bid)
    $41 Avg Bid
    6 bids
    Bid now
    Experts on Communication system, Digital Signal Processing, and Matlab needed Ended
    VERIFIED

    Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks

    Electrical Engineering Engineering Matlab and Mathematica Telecommunications Engineering Verilog / VHDL
    $26 (Avg Bid)
    $26 Avg Bid
    3 bids
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    Mips, Verilog project Ended
    VERIFIED

    Small project on computer architecture

    Verilog / VHDL
    $28 (Avg Bid)
    $28 Avg Bid
    20 bids
    Bid now
    State Machine and Timing Diagram for Embedded System Ended
    VERIFIED

    State Machine and Timing Diagram for Embedded System. More details to be provided.

    Embedded Software Verilog / VHDL
    $60 (Avg Bid)
    $60 Avg Bid
    17 bids
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    OS work ( Printing Service) Ended
    VERIFIED

    In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov...

    C Programming C++ Programming Java Programming Verilog / VHDL
    $43 (Avg Bid)
    $43 Avg Bid
    8 bids
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    Systemverilog TCPIP model Ended

    Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL.

    Verilog / VHDL
    $246 (Avg Bid)
    $246 Avg Bid
    3 bids
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    NS3 simulation using c++ and ubunto NS3 simulator Ended
    VERIFIED

    NS3 simulation using c++ and ubunto NS3 simulator

    C Programming C++ Programming Linux Software Architecture Verilog / VHDL
    $482 (Avg Bid)
    $482 Avg Bid
    5 bids
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    ns3 project c++ ubunto needed Ended
    VERIFIED

    i need this simulation for ns3 using c++

    C Programming C++ Programming Linux Software Architecture Verilog / VHDL
    $312 (Avg Bid)
    $312 Avg Bid
    4 bids
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    Simple SCADA WEB page Ended

    Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview

    Engineering LabVIEW PHP Software Architecture Verilog / VHDL
    $239 (Avg Bid)
    $239 Avg Bid
    9 bids
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    Vhdl coding for a small project Ended

    1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output

    Verilog / VHDL
    $42 (Avg Bid)
    $42 Avg Bid
    4 bids
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    Serial Interface using Python Ended

    Design a serial interface using Python for communication with FPGA.

    FPGA Python Software Architecture User Interface / IA Verilog / VHDL
    $42 (Avg Bid)
    $42 Avg Bid
    5 bids
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