Verilog / VHDL Jobs
Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC). 1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible. 2. Read bus should read the address to be transferred. 3. The write bus should transfer the PSS signal or the chip select...
Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC). 1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible. 2. Read bus should read the address to be transferred. 3. The write bus should transfer the PSS signal or the chip select...
I need you to debug a module in vhdl for me. I would like this to be developed quickly
the project is a small task to be done on AVR i will share more details in the chat. Expert only
Implement a Matlab gui with sFFT/sMFCC
I have a few mini projects to be done using Quartus II IDE. Experts place bid on the project and I will share more details in chat.
Create an equalization in Simulink using given wxamples.
Communication using PPM modulation scheme using MSP430
I need help in DSP(Digital signal processing) project
I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.
I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max
I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.
I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.
Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...
The Project is to develop Verilog code to control DDR4 DRAMs via a Memory Controller and I2C interface using a Xilinx Zync+ UltraScale FPGA.
Looking for VLSI experts having strong digital electronics and verilog concepts
Looking for vlsi frontend experts with strong basics in digital electronics
Risolvere un esercizio di VHDL semplice in cui si utilizza sensori, timer e altri circuiti standard. Per maggiori informazioni contattatemi in messaggio privato. Massima serietà, molto importante la professionalità e conoscere bene il linguaggio di programmazione.