Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    18 jobs found, pricing in SGD

    Temperature control project on MC9S08GB32 using code warrior and i have previous year solved solution as well more details will be shared

    $187 (Avg Bid)
    $187 Avg Bid
    8 bids
    ALU design in VHDL 6 days left
    VERIFIED

    mini arithmetic logic unit for signed and unsigned numbers

    $23 (Avg Bid)
    $23 Avg Bid
    6 bids

    Looking for a Senior Physical Design Engineer in California only

    $47743 (Avg Bid)
    $47743 Avg Bid
    1 bids

    DESIGN OF NAND MEMORY CONTROLLER ARCHITECTURE FOR BIG DATA STORAGE

    $41 - $341
    $41 - $341
    0 bids

    I am looking for an engineer who has good knowledge of Codesys for Programmable Logic Controllers (PLC). The freelancer must have experience of doing technical writing as well. More details will be shared with the shortlisted freelancer.

    $217 (Avg Bid)
    $217 Avg Bid
    4 bids

    Hello Everyone I am looking for an Engineer with sound knowledge of CODESYS for completion of project. More details will be shared with experienced and interested freelancers. The person must have sound knowledge of technical writing as well to handle the description part of the project. Kindly place your competitive bids for further discussion.

    $125 (Avg Bid)
    $125 Avg Bid
    9 bids

    Project Description: 2-Stage Project with 2 milestone payments. 1. The 1st stage is completion of the board design (must use Orcad/Cadence software), which includes schematic, printed circuit board and Bills Of Materials. 1st milestone payment on successful completion of 1st stage 2. The 2nd stage is coding the software with good documentation and 2nd milestone payment is made on successful c...

    $870 (Avg Bid)
    $870 Avg Bid
    45 bids

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

    $5215 (Avg Bid)
    $5215 Avg Bid
    17 bids
    ADC in FPGA 2 days left
    VERIFIED

    Implementation of suitable RC filter for ADC. Digital part implementation is done on FPGA. RC filter has to be designed for given specification.

    $30 (Avg Bid)
    $30 Avg Bid
    8 bids

    VHDL code of optimization algorithm fixing.

    $80 (Avg Bid)
    $80 Avg Bid
    9 bids

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $228 (Avg Bid)
    $228 Avg Bid
    3 bids

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $36 (Avg Bid)
    $36 Avg Bid
    2 bids

    i want to design step by step antenna by CST program (spiral antenna) by TeamViewer you will describe to me how to design it

    $164 (Avg Bid)
    $164 Avg Bid
    14 bids

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $230 (Avg Bid)
    $230 Avg Bid
    3 bids

    Hello Please check it carefully. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ......................................................... [login to view URL] have a look here, at the moment I need only labaa 3. maybe you have to download the files because ...

    $31 (Avg Bid)
    $31 Avg Bid
    2 bids

    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

    $407 (Avg Bid)
    $407 Avg Bid
    2 bids
    VHDL Verilog 5 days left
    VERIFIED

    Kann mir jemand helfen dieses Verilog Problem zu lösen?

    $52 (Avg Bid)
    $52 Avg Bid
    2 bids