Altera de2 qsys jobs

Stepper Motor Controller with DE2 board, write vhdl codes, compilation, and simulation.

In order to do the project, you will need Altera's DE2-115 Board. Please contact me for more info. Prior work with MicroC/OS-II RTOS with the Nios II Processor is an asset.

I want to generate square wave by using verilog on Altera DE1-SoC and MTL2 with changing the frequency and Duty cycle

Assembly and C for Altera. Timers and Interrupts. More details to be provided.

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an automobile tail-light control unit is designed on the Altera board. The automobile has two sets of four tail-lights in a row. For the turn right signal, the right sided tail-lights flash in the sequence from right to left. For the turn left signal, the left sided tail-lights flash in the sequence from left to right. There is a half a second pause between each step. Turning on both the L and R signals makes all eight lights flash on for half a second and off for half a second, corresponding to the emergency flash signal. When the L and R signals are off and the B signal is on all eight lights turn on to indicate braking. If the turn right R signal is on and the B signal is pressed then the right tail-lights follow the sequence and the left tail-lights are on to indicate ...

Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details.

I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask you one question. What version of Altera Quartus did you use and how did you manage to compile it?

A catchy name for a system we will market to business that has a) video calling b) phone calling c) messaging - Has to a single word eg Zoom (but not Zoom!) - Not have "com" in there - Be less than 9 letters - Target businesses - Can Be adventurous- name does not need to actually have anything do with calling etc. Has to sound catchy eg Altera or something to that effect !

Montar 10 (dez) variações do anúncio. (Leia o item IMPORTANTE abaixo) são 10 modelos de imagens para publicidade no facebook com texto. IMPORTANTE: O Texto é Padrão, só altera o produto oferecido e a imagem do fundo. Para aprovação do projeto pode ser feito apenas 2 ou 3 modelos para eu ver como eles vão ficar, após a aprovação os 10 devem ser entregues para conclusão e liberação do pagamento. Preciso dos 10 arquivos editáveis de maneira que eu possa editar depois... Preciso dos 10 arquivos em PNG para eu publicar no facebook O Designer tem total autonomia para criar e desenvolver conforme sua ideia, caso queira uma dica, eu pensei numas imagens q...

I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code

Hello, i want to create project using altera DE2-115 board to detect edges on 3 image using sobel filter and show they ober VGA 640x480. To choose which image should be apear is needed 2 swtich. i have done some algorithm with matlab and now i have to implement it on altera. Thanks

i need to port existing TARP OpenHPSDR-Firmware to new hardware have many change to make 1-) migrate from Altera to Xilinx ZedBoard Zynq-7000 2-) ADC chip swap AD9467 ( 2 x original clock speed) 3-) low speed Audio part ADC/DAC no need to be ported at this time 4-) use MAC and PHY of the ZedBoard 5-) all code need to releasable into open source link to original source code (ANAN-10%20and%20100) both ADC DAC will be provided as a FMC card once work on the ZedBoard project will move to a new board whit PCIe interface this is to be considered but it on a different project be a ham radio operator is a great advantage on that project

Design a digital system that will generate police or unbalance siren sound

Hii. I want someone can write verilog language and this vedio have 10 mode ,,I want 5 mode of the same video ,,my blackpord is "DE1 ALTERA".

does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files.

build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Acc...symbol on a schematic diagram and connected together using wires. Accompanied with each unit should be a functional waveform for verification. It is also mandatory that any four units be connected together or working together using only Verilog HDL, then that design can be placed as a symbol on a schematic diagram. Use Quartus to build your project. Your design need to also be verified on the DE2-115 FPGA Alt...

1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic

I have a dc motor with optical encoder that produces 360 pulse per revolution. I need fuzzy logic control of this motor. Altera de2 does not have an ADC so I have to use external ADC (max1132) to read set value from potentiometer. The set value and current RPM should be displayed on DE2's LCD.

I need you to develop some software for me. I would like this software to be developed . i need some one to write a basic altera program onEPM3128ATC100-10N for live feed for a sign board

esign a multi-cycle implementation of the reduced MIPS architecture and implement it on the DE2-115 board. You will need to add I/O to the approach discussed in the text. Add the following peripherals: interrupt system connected to a push button, slide switches, green LEDs, red LEDs, and the 7-segment display. Develop a test program to verify you machine works and run it on the simulator and on the board. The design can be based on the system in the text but you should maximize the use of behavioral code as opposed to the approach used in the text. The control unit and the alu should be done behaviorally at a minimum. Provide a report which documents your design, implementation and results. Include data from simulations in the form of screen captures, photos, etc.

Hi, We are engineering consultancy and IT firm. We need some IT guys for some small tasks. We would make long term relati...the best one. Below is the task details: The total word count is limited around 2000 (±10%). 1. Introduction to Nios II softcore processor: (30%) A simple design and build a Nios II softcore processor on FPGA. Write a short, properly structured technical report. 2. Customisation of Nios II softcore processor: (30%) An introduction to customising Nios II softcore processor using Qsys. Write a short, properly structured technical report. 3. Computer peripherals: (40%) A simple design exercise of configuring peripherals for Nios II softcore processor. Write a short, properly structured technical report.   Submission: 48 hou...

I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card.

THis must implement on quartus( altera FPGA cyclone IV)

Hello ahmed! I am masters student pursuing, computer engineering. I don’t have any abstract but I would like to implements something on image processing and altera

I need some one to develop some software Altera Quartus for me.

I need some one to develop some software Altera Quartus for me.

I need some one to develop some software Altera Quartus for me.

I need some one to develop some software Altera Quartus for me.

Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers

AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the required peripherals on the list, please discuss with the lecturer as soon as possible. • Ultrasonic range finders XL-MaxSonar-EZ/AE MB1200 • Microphones, Speakers • Infrared remote controls • PAL Camera device (limited numbers) • PS/2 keyboard (limited numbers) Note that the audio peripherals on the board may be used as general purpose analogu...

FPGA design ( actually MAX V CPLD). Requires good knowledge of Altera Quartus II manual layout, routing, schematic capture. Altera serial ( RS232 or SPI) and Gray counters IP library blocks will be used. Will work interactively with the designer.

We are looking for a FPGA developer with solid experience in Altera FPGAs. This is a small project, and we will hire you on an hourly rate. Please reply back and share your experience with Altera FPGAs as well as your hourly rate. Thank you

Ihave a project that has been already designed, Schematic, PCB as well as software. I need someone who is familiar with the Altera and Atmel chipsets. All that is required is the PCB loading, the flashing of the Altera and Atmel chips and the final testing. All documentation and video's of the working prototype's can be made available. This project has been sitting idle because the designer has gone missing. Budget for the completion of this task can be negotiable as this would be an ongoing production run once all has been sorted out hence the budget has been set as "Very small budget" more information and documentation can be made available upon request. Would like to start on this project at the end of Semptember 2017.

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We need a modification to an Ettus USRP SDR FPGA code. We have a working system and reference for a 1 TX and 1 RX system, using half of the USRP1, including the source files for the FPGA code and corresponding c library. We have working FGPA code for a 2 TX and 2 RX system, and but need about 15 lines of verilog code ported from the 1 TX and 1 RX system to the 2 TX and 2 RX system. Also, we need the working c libary in the transceiver (1 Tx and 1 RX) modified to support the 2 TX and 2 RX configuration, which should require about 20 - 40 lines of c code changes. All work can be completed remotely, and we would make available a reference 1TX and 1RX system (with all source code), and a development environment for the 2TX and 2RX system (where you could test your modified FGPA code and c ...

The purpose of the switch is to switch video stream of Altera's VIP protocol from any input to any output. Each output can receive only one stream at a time. One input can be broadcasted to multiple outputs. Detailed requirements document attached. Only experienced freelancers with reviews

please check the attached file . I want to complete using quartus tool to install it on fpga altera kit in 3 hrs max

Training using Verilog Altera-Quartus

... I2S interface (for audio) For lower bids will provide ip that needs to be hooked up Using Verilog Using Altera (Cyclone V SoC) Interface with Avalon Bus (maybe master) Write to DDR3 Simple C/C++ code to access the data from linux or like Bare metal code. something to do with DDR3 storage from avalon Bus Requirements: BCLK runs 16MHz1 left and right channel is 16 bits sample each side I have Started the Verilog code, or will provide you with opensource i2s ip. Please do provide me with information how to load on QSYS how to run the testbench to test it's working. This will be my guide to learn how to use Altera and learn FPGA. I'm using a cyclone V SOC (Altera dev kit soc), but any you can implement in other if needed, i can re...

Interfacing an Altera FPGA to a Windows PC to transmit data over TCP/IP protocol (1000MB Ethernet).

Hi, We are looking for expert, who can help us to design Hardware for Video Encoding based on FPGA (Xylinx & Altera) or Microcontroller (MAXIM) with Full service. Only Expert Can dont waste time please.

Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much

Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much

camera system on Altera Cyclone V

IL electonics company needs board & layout designer. Job description: Development of Altera Arria10 Soc computer board (As carrier board), providing us with circuit, layout, gerber & documentation. please send hourly rate

need to design packet generator according to input parameters (function) and compare checker of received packets according to parameters the generator/tester should be able to generate all UDP/TCP/IP fields including options for TCP/IP code should be readable, modular, well commented and easy to maintain in future target to verify ALTERA FPGA with TSE MAC

Please help with this Project; The design that is being asked to simulate is uploaded with the file as a jpg; called Design_1.jpg. The question is asked: Proceed with the design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. Implementation with other class of devices, like 71LS161/163 will not be considered. The simulations should use a clock of 25 MHz . You can sketch it or design it on paper. That is fine.

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i want to monitor power on the fpga board. its MAX 10 NEEK board from altera. The task is to monitor the voltage rails when a load is running on the board. The load will be different video signals being run on the lcd of NEEK board. HDMI in is recieving video from either HDMI player or just directly from a laptop HDMI out .could be a video played on youtube or VLC player. There is a code which displays the video on the LCD successfully. There is another example code for power monitor when there is no load running on the board. Instantiation of one needs to be done with the other.