MPEG-TS router on FPGA - serial/parallel TS input, parallel TS out, AES128 CBC crypto, PCIe interface

Looking for someone who can help to implement taking several serial MPEG2TS streams (up to 50-60mbit per stream), up to 4-8 streams (can be less depending on hardware capability), do some rudimentary PID filtering (for example dropping NULL packets), provide (optional) AES128 encryption with fixed key, and ability to stream over PCIe. Host side driver development is NOT needed, however some basic testing will be required to prove the design. I may open another project for the host driver development, unless a reference design driver can be quickly adapted.

Target FPGA - Lattice ECP3 w/PCIe IP

Using LFE3-35EA-VERSA-EVN Evaluation board (can be dropshipped to user after skill confirmation)

mspaint diagram is provided - more details can be explained over chat. Preferably looking for someone who has done PCIe with ECP3 (obviously) and has a general understanding of mpeg transport stream, PID filtering, etc.

Budget is flexible, priority is actually getting the work done.

Other possible devices to be considered:

1) Altera EP4CGX15BF14C8N. This is currently the most likely choice due to cost/avaiability
2) Lattice ECP5 series - LFE5UM-45F-8BG381C. This part is 2x the cost of Altera tho.

FPGA Verilog / VHDL

Project ID: #13774664

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