8 Years Experience in digital system design using VHDL/Verilog for FPGA's and CPLD's in Xilinx Family boards and Custom ASIC Boards.
Specialties
SystemVerilog, SystemC, VERILOG and VHDL, TCL/TK scripting, PERL Scripting.
Synopsys Design Compiler, IC Compiler, VCS.
Xilinx ISE , Vivado, Xilinx Chipscope Pro.
Cadence Virtuoso, NC-Verilog, Simvision, SoC Encounter
Mentor Graphics ModelSim 10, Questa Sim, Calibre Design REV, DRC, LVS, PEX.