HI,
I have more than 11 years of professional experience in ASIC/FPGA Design and Verification.
- RTL development using Verilog/VHDL/SpinalHDL, knowledge of SERDES, AXI4 based FPGA logic design, Formal Verification, Assertions.
- RTL development of USB2.0 Soft PHY IP.
- RTL development of USB2.0 to Peripherals (I2S, SPI, I2C, UART)
- Development of Systemverilog/UVM environment from scratch.
- Verification architecture development and testplan writing.
- Implementation of reusable Universal Verification Components (UVC) and VIP.
- Debugging simulation and regression failures.
- Code coverage and Functional coverage analysis and closure.
- MIPI, C-PHY, D-PHY, USB2.0, DDR2, AXI4, AXI4 Stream protocols.
- FW Tests implementation in C to verify processor based subsystems.
- Translating C++ Model of VESA DSC (Display Stream Compression) Decoder into RTL logic design using SpinalHDL/Verilog.
- UVM RAL (Register Abstraction Layer) implementation and integration.
Thanks,
Kartik