ALU design in VHDL

Greetings, Hope you are doing well. I am computer architecture designer and I happen to have 32-bit ALU in VHDL and Verilog. It supports the following features: add, sub, sll ,slt ,sltu, xor, srl, sra, or, and, mul, mulw, mulh, mulhu, mulhsu, div, divw, divu, rem, remw. I can change parameter sizes (1-bit to 128-bit) as per your requirements. Can provide ModelSim simulations and hardware testing on Altera DE-01 board. Will deliver in 1 day. Also let me know if any thing else is required. Looking forward to first project at freelancer with you. Regards, Abdullah

Dear sir I have more than 10 years experience in digital design using vhdl please check my profile also please message me so that we can discuss

I am EE engineer.I have lots of experiences working with Xilinx and Altera FPGA boards writing VHDL and embedded C for NIOS II (field of interest). I have background in digital design. Also worked with micro controllers such as msp430. We can discuss it more in chat. Regards,

Hi, glad to bid on your project. I’m an expert on Data Science, Machine Learning, and Artificial intelligence etc... I m a Doctorate in Engineering , I have read your description, i have a 18+ years of experience on development and research papers solutions . good at Matlab & Simulink , Python R VHDL Verilog Spice software programming with Numerical analysis CFD Applications for mechanical and electrical

I'm doing computer engineering, this was my assignment in previous semester. And if you want it's solution, I can send it to you.

Hello there, I am an Electrical Engineer by profession and specialist in electronics and embedded systems. I have strong expertise in Verilog and VHDL using FPGA's. I have already completed your above mentioned project sucessfully for one of my client. I have a running VHDL ALU code and i can deliver you suoer quickly. Let's discuss it over inbox if you have any additional specifications to it. If you have any questions you can ask me. Looking forward to hearing from you. Regards, Waqar Shahzad

hello, hope you're doing well, i'm an embedded systems engineer and i already have an ALU design written in VHDL, wich will save you a lot of time. i need just to adjust it according to your specifications. thank you.

Respected sir , I am VLSI post graduation student who has full grip on Both VLSI FRONT END AND BACK END IF you give me this project I will design the circuit which reduces the Power and delay

1. Write an mini ALU using Verilog . 2. Customize it for the required FPGA 3. Will simulate it with the VIVADO

Hi, I have Masters degree in VLSI Design with IEEE publications.... the module you require are already made up and ready with me.....I can give it to you instantly. ping me for details.