Verilog code fbga parking spot counter

Hello I am an electronics engineer with a strong knowledge of verilog and digital designing. I have done a lot of work related to this field. I know the user the divisers for downscaling the internal clock of FPGA. Thank you.

I have 8 yr experience in design & Verification using verilog/vhdl/UVM/OVM can design & deliver this on time ...

I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.