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VHDL implementation of CAVLC Decoder on FPGA

₹600-1500 INR

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almost 8 years ago

₹600-1500 INR

Paid on delivery

i need a VHDL implementation of CAVLC Decoder. The code must be tested on Altera cyclone 2 [login to view URL] can use seven segments or LCD to display output.

Project ID: 10757668

About the project

4 proposals

Remote project

Active 8 yrs ago

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4 freelancers are bidding on average ₹3,546 INR for this job

Flag of PAKISTAN

No issue.. Br, Rb

₹4,444 INR in 3 days

5.0

(6 reviews)

3.3

3.3

@rohi1710rohi1710

Hi , I am working as FPGA design engineer since last 7 years and I have expertise in both verilog and VHDL. I can help you in this project with greater accuracy.

₹6,666 INR in 7 days

4.9

(3 reviews)

3.5

3.5

Flag of PAKISTAN

I have a great experience in this field. Kindly contact me now and I’m sure we will make a reasonable deal thanks a lot.

₹8,888 INR in 10 days

5.0

(1 review)

1.6

1.6

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About the client

Nagpur, India

5.0

2

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Member since Jul 31, 2013

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