Closed

design with Altera FPGA

4 freelancers are bidding on average £232 for this job

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a More

£250 GBP in 3 days
(89 Reviews)
6.4
Softeria

I am Electronics Engineer. My Expertise are MATLAB, Simulink, AUTO CAD, Pro E, Verilog, Python, PSSE, PWS, PSS Sincal, ORCAD, Altium(PCB design pursuit) ,MPLAB, Xilinx (VHDL, HDL). PLC, SCADA Systems, Wireshark and pac More

£150 GBP in 3 days
(5 Reviews)
4.1
tienthanhkt09

Hi there, I have experienced in VHDL design and Timing closure analysis. I also familiar with Xilinx and Intel tools design. please take a look via my profile. thanks.

£277 GBP in 4 days
(0 Reviews)
0.0
asicdsm

I can compile with Precision RTL and/or Synplify. Do you have the constraints defined in plain text ?

£250 GBP in 1 day
(0 Reviews)
0.0