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risc processor design and test ,vhdl

$30-250 AUD

Closed
Posted over 5 years ago

$30-250 AUD

Paid on delivery
risc processor design and test, more detail I will provide on chat
Project ID: 17894748

About the project

11 proposals
Remote project
Active 5 yrs ago

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11 freelancers are bidding on average $170 AUD for this job
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Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
$144 AUD in 1 day
4.9 (94 reviews)
6.9
6.9
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A highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, VLSI/CMOS Design, Cadence ADE, /Virtuoso/Layout/Digital ASIC Design from RTL-GDSII. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other projects
$166 AUD in 3 days
4.9 (165 reviews)
6.8
6.8
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Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. (You can refer to my portfolio) The project sounds really challenging which makes it much more appealing. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam
$120 AUD in 3 days
5.0 (7 reviews)
4.5
4.5
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**I never compromise on quality. Price can be negotiated** Hi, I'm FPGA design Engineer with three years of Experience designing and implementing FPGA based systems specially soft processors like RISC, MIPS, CISC, and GPUs. I can give the perfect risc processor design with test system. Please contact me for details. thanks
$200 AUD in 3 days
4.6 (24 reviews)
4.3
4.3
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we already have experience with designing risc processors such as MIPS.
$188 AUD in 8 days
5.0 (6 reviews)
4.1
4.1
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i HAVE WELL EXPERIENCED IN DOING SUCH KIND OF JOBS.......................................AND I WILL DO MY LEVEL BEST..........
$155 AUD in 5 days
0.0 (0 reviews)
1.3
1.3
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I have 5 year of experience in RTL design and Test bench writing in VHDL/ Verilog/ System verilog . Handled many FPGA related project from RTL design( in both Verilog/VHDL) to bring up . worked on : UART,I2C,SPI,Ethernet(RGMII,XGMII),DDR3,DAC,SERDES.. Thank you.
$222 AUD in 3 days
0.0 (0 reviews)
4.4
4.4
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I have been doing such projects for my students
$155 AUD in 5 days
0.0 (0 reviews)
0.0
0.0
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I am a master student in instrumentation, and have conducted research and several international journals
$111 AUD in 3 days
0.0 (0 reviews)
0.0
0.0
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Hello dear Sir, I have designed and implemented an 8-bit RISC CPU using basic logic ICs, during my 2nd year of Bachelors in Computer Engineering. Currently I am in the final year and I assure you that I have earned a lot of experience and confidence from that single project. I have also done many other digital electronics projects. The purpose of that project was demonstration of components of a CPU, that normaly wouldn't be possible by any other means. I have got an award for best project of the college for the same project. I am eagerly waiting for your positive reply. Thanks and regards.
$155 AUD in 3 days
0.0 (0 reviews)
0.0
0.0

About the client

Flag of INDIA
Delhi, India
5.0
49
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Member since Oct 5, 2014

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