Design and Verification of USB 3.0 for SuperSpeed Data Transfers

Cancelled Posted Dec 15, 2014 Paid on delivery
Cancelled Paid on delivery

I want someone to code Physical and Link Layer of USB 3.0, and develop a verification environment for it using System Verilog.

Verilog / VHDL

Project ID: #6868936

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2 proposals Remote project Active Dec 16, 2014

2 freelancers are bidding on average ₹7777 for this job

magdycz55

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