A single precision floating-point adder (FP ADD)
$250-750 USD
Paid on delivery
A single precision floating-point adder (FP ADD)
For the design you need to do the following:
- Model it in Verilog HDL language
- Create a test bench for verification of the developed design
- Synthesize your design using the Xilinx FPGA synthesis tool
Scoring criteria:
- Design functionality
- Testing comprehensiveness
- Synthesized design area
- Synthesized design speed
Project ID: #5891735
About the project
18 freelancers are bidding on average $472 for this job
Dear sir I have more than 7 years experience in digital design using fpga I know exactly how To design floating point adder and perform all required simulations and analysis using xilinx ise
I can help you right away! Please accept my bid to begin working at your project! I can finish your project in 4 hours maximum! Hello! If you have digital design projects I can help you right away! I have 8 years More
I am having 10+ Years of experience in the same area but one thing I can do this job for you , I have xilinx ISE 14.2 with me . please let me know when and how can we discuss this further ? I am available on skype a More
Dear mariam, I am interested in undertaking your project. I have large experience with both VHDL and Verilog HDL as a seasoned expert for more than 15 years. The design will be implemented in Verilog HDL adhering to th More
Have been working in C and VHDL for a very long time . Can provide better 24 Hour customer support. I have a team that can finish your work very soon.
Hi, I am an Electrical Engineer recently graduated and currently working in the Embedded Industry. I am skilled with hardware design in Verilog HDL. I designed a simple RISC processor in my Digital Design course usi More
I can deliver the code for you in 5 working days. I will respond to all requirements stated in the project description. Regards, Botond
Hi, I will be able to implement it in VHDL on a Nexys 3 FPGA borad (Spartan 6), with which I already have experience and I will be glad to get more details about the project. Regards, Alon
I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset More
I wrote code IEEE 754 32 bit FP_adder system verilog design code and verilog testbench code. I have stimulus with only two positive floating number. I have simulated it with modelsim. If you want it, I can give it More