A single precision floating-point adder (FP ADD)

Closed Posted May 3, 2014 Paid on delivery
Closed Paid on delivery

A single precision floating-point adder (FP ADD)

For the design you need to do the following:

- Model it in Verilog HDL language

- Create a test bench for verification of the developed design

- Synthesize your design using the Xilinx FPGA synthesis tool

Scoring criteria:

- Design functionality

- Testing comprehensiveness

- Synthesized design area

- Synthesized design speed

C Programming Java Verilog / VHDL

Project ID: #5891735

About the project

18 proposals Remote project Active Jun 9, 2014

18 freelancers are bidding on average $472 for this job

ahmedmohamed85

Dear sir I have more than 7 years experience in digital design using fpga I know exactly how To design floating point adder and perform all required simulations and analysis using xilinx ise

$333 USD in 7 days
(394 Reviews)
7.8
trustus

Hello , We have a team of Skilled Java-J2EE professionals with experience up to 8 yrs. You will be able to directly communicate with our technical expert. Our Expertise is J2EE: 1) Frameworks: Struts More

$299 USD in 10 days
(122 Reviews)
7.7
theincredible

A proposal has not yet been provided

$1578 USD in 10 days
(94 Reviews)
6.8
zarnescugeorge

I can help you right away! Please accept my bid to begin working at your project! I can finish your project in 4 hours maximum! Hello! If you have digital design projects I can help you right away! I have 8 years More

$250 USD in 0 days
(45 Reviews)
5.8
shobhitkapoor

I am having 10+ Years of experience in the same area but one thing I can do this job for you , I have xilinx ISE 14.2 with me . please let me know when and how can we discuss this further ? I am available on skype a More

$555 USD in 15 days
(17 Reviews)
4.5
kaveirious

Dear mariam, I am interested in undertaking your project. I have large experience with both VHDL and Verilog HDL as a seasoned expert for more than 15 years. The design will be implemented in Verilog HDL adhering to th More

$250 USD in 5 days
(4 Reviews)
4.4
smk55

Hi mariam91 I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience in digital design and well acquainted with ISE, NCverilog, EDK embedded tools. More

$555 USD in 10 days
(4 Reviews)
3.4
nadeemsajjad

Have been working in C and VHDL for a very long time . Can provide better 24 Hour customer support. I have a team that can finish your work very soon.

$277 USD in 10 days
(3 Reviews)
3.0
kiran469

I had masters in VLSI and lot of experience in verilog/vhdl. I had worked on single and double precision floating point multipliers as my thesis work. so i can complete your project with in one day .Check my profile i More

$250 USD in 0 days
(1 Review)
2.3
mohsinelec

Hi, I am an Electrical Engineer recently graduated and currently working in the Embedded Industry. I am skilled with hardware design in Verilog HDL. I designed a simple RISC processor in my Digital Design course usi More

$277 USD in 4 days
(2 Reviews)
2.1
botondkireivw

I can deliver the code for you in 5 working days. I will respond to all requirements stated in the project description. Regards, Botond

$250 USD in 3 days
(5 Reviews)
2.8
komals01

FP addition is a tricky and each part(sign , exponent and fraction)needs to be handled precisely it involves the following steps: => de-normalization => addition => normalization Having functions for each of th More

$300 USD in 10 days
(0 Reviews)
0.0
devinedreams

A proposal has not yet been provided

$750 USD in 20 days
(0 Reviews)
0.0
AlonSidi

Hi, I will be able to implement it in VHDL on a Nexys 3 FPGA borad (Spartan 6), with which I already have experience and I will be glad to get more details about the project. Regards, Alon

$555 USD in 4 days
(0 Reviews)
0.0
keyurmahant

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset More

$555 USD in 10 days
(0 Reviews)
0.0
hyungoktak

I wrote code IEEE 754 32 bit FP_adder system verilog design code and verilog testbench code. I have stimulus with only two positive floating number. I have simulated it with modelsim. If you want it, I can give it More

$355 USD in 2 days
(0 Reviews)
0.0