Adding support to the NeTV device for DVI resolutions (Verilog code modification for Xilinx Spartan-6 FPGA)

The NeTV is a piece of Open Source hardware which takes a HDMI signal in and allows custom images and text to be overlaid on the image before output. More information about the device can be found in the detailed information section. This project is to add support for common DVI resolutions to the Verilog code found at <[login to view URL]> The resolutions that need to be added are; * 1024x768 @ 60Hz, 75Hz and 85Hz * 1280x720 @ 60Hz, 75Hz and 85Hz * 1280x800 @ 60Hz, 75Hz and 85Hz * 1366x768 @ 60Hz, 75Hz and 85Hz **The code will be tested by downloading the new firmware into a stock NeTV and trying to use the overlay feature on a DVI signal via passive DVI->HDMI and HDMI->DVI changers.** ## Deliverables To complete this project you may need to purchase a NeTV. **Make sure you include the cost of all hardware in your quote. **The result of this project will be released under the same licenses to the NeTV device it's based on. This is an FOSS project, reusing compatible source code is compatible is not only allowed, but recommend! NeTV Device The NeTV can be purchased from AdaFruit at [[login to view URL]][1] The device contains a Xilinx Spartan FPGA to do the HDMI processing and a Marvell ARM chip to push the overlaid images into the FPGA. More information, including full schematics and Xilinx code can be found at the following URLs; * [[login to view URL]][2] * [[login to view URL]][3] * [[login to view URL]][4] # Notes The major, but tangential, problem you'll encounter is that the overlay framebuffer's resolution support only matches those of major CEA resolutions. A laptop will generate resolutions that are decidedly not CEA compliant (i.e., nobody makes TV content at 1024x768), which as a pass-through the NeTV is perfectly fine to allow but we don't have the timings programmed to match that on the overlay. We handle that case by cutting the feed and forcing the NeTV into a self-timed 720p mode.